intel / rohd

The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
https://intel.github.io/rohd-website
BSD 3-Clause "New" or "Revised" License
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Generate RTL for both classes even when two classes have identical contents #394

Closed sshankar4 closed 9 months ago

sshankar4 commented 1 year ago

Describe the bug

Two classes with same contents:

class my_mod extends Module {
  my_mod(Logic clk, {String name = "my_mod"})
      : super(
            name: name, definitionName: "my_mod", reserveDefinitionName: true) {
    addInput('clk', clk);
  }
}
class my_mod_copy extends Module {
  my_mod_copy(Logic clk, {String name = "my_mod_copy"})
      : super(
            name: name,
            definitionName: "my_mod_copy",
            reserveDefinitionName: true) {
    addInput('clk', clk);
  }
}

instantiated under SoC as,

class Soc extends Module {
  Soc(Logic clk) : super(name: 'soc') {
    clk = addInput('clk', clk);

    **my_mod**(clk, name: "**mod_inst**");
    my_mod_copy(clk, name: "mod_inst_copy");
 }
}

RTL generated is:

module Soc(
input logic clk
);
**my_mod_copy**  **mod_inst**(.clk(clk));
my_mod_copy  mod_inst_copy(.clk(clk));
endmodule : Soc

mod_inst is supposed to be the instance name of class my_mod but that's not the case with generated RTL.

To Reproduce

Use the provided three classes, my_mod, my_mod_copy and soc and generate RTL with them

Expected behavior

module Soc(
input logic clk
);
**my_mod**  **mod_inst**(.clk(clk));
my_mod_copy  mod_inst_copy(.clk(clk));
endmodule : Soc

Actual behavior

module Soc(
input logic clk
);
**my_mod_copy**  **mod_inst**(.clk(clk));
my_mod_copy  mod_inst_copy(.clk(clk));
endmodule : Soc

Additional: Dart SDK info

Dart SDK version: 2.18.3 (stable)

Additional: pubspec.yaml

No response

Additional: Context

No response

mkorbel1 commented 1 year ago

Perhaps related to #345

mkorbel1 commented 9 months ago

This was fixed in #440