SystemVerilog has some weird rules about when you can take a bus subset/slice (e.g. you cannot take a slice on an expression). The current implementation in ROHD marks "original_..." as not unpreferred so to avoid the signal being eliminated so that a slice is not taken on an expression. If there's a bus-subset with no expression, however, then we add an extra assign statement in the generated SystemVerilog for no reason.
Desired solution
Detect when it's required to have a separate assign statement and only keep it there in those cases. This will make the generated SV a little prettier and reduce clutter of unnecessary intermediate signals.
Alternatives considered
No response
Additional details
This is probably tricky to figure out for all cases and to implement properly. This is not a functional issue, only style.
Motivation
SystemVerilog has some weird rules about when you can take a bus subset/slice (e.g. you cannot take a slice on an expression). The current implementation in ROHD marks "original_..." as not unpreferred so to avoid the signal being eliminated so that a slice is not taken on an expression. If there's a bus-subset with no expression, however, then we add an extra
assignstatement in the generated SystemVerilog for no reason.Desired solution
Detect when it's required to have a separate
assignstatement and only keep it there in those cases. This will make the generated SV a little prettier and reduce clutter of unnecessary intermediate signals.Alternatives considered
No response
Additional details
This is probably tricky to figure out for all cases and to implement properly. This is not a functional issue, only style.