Avoid module creation for simple constant scenarios in gates

[mkorbel1]

Motivation

Sometimes it's easy to initialize some variable to 0 or 1, and then do multiple operator functions on it afterwards like &, ~, and |. There are some common rules that we can use to avoid creating gates when not necessary. For example:

• ~0 == 1 (inversion of a constant is constant of inversion)
• (x & 0) == 0
• (x & 1) == x
• (x | 0) == x
• (x | 1) == 1

Skipping over these scenarios would allow for boosts in simulation performance and cleaner generated verilog.

Desired solution

Modify the operator overrides in Logic to avoid creation of Modules if it can instead directly compute a Logic to return (like in above situations).

Note that this won't completely avoid all the applicable scenarios alone since there could be things like 0 assigned to another signal which is then used in a gate. Perhaps some optimization in the generation of verilog after assignment collapsing could help even more.

Alternatives considered

No response

Additional details

No response

[mjayasim9]

Will work on this!

[mkorbel1]

We should probably make it impossible to put onto a Const to avoid weird surprises when this optimization happens