Sometimes there's a bunch of different independent hierarchies that we want to generate SystemVerilog for. If we generate them with independent SynthBuilders, then any shared sub-modules may be declared with the same definition name, causing issues building all them together.
Desired solution
Make it possible to pass multiple independent top-level Modules to a SynthBuilder to generate code that is uniquified properly across all of them.
Motivation
Sometimes there's a bunch of different independent hierarchies that we want to generate SystemVerilog for. If we generate them with independent
SynthBuilders, then any shared sub-modules may be declared with the same definition name, causing issues building all them together.Desired solution
Make it possible to pass multiple independent top-level
Modules to aSynthBuilderto generate code that is uniquified properly across all of them.Alternatives considered
No response
Additional details
No response