Previous changes made any invalid value on a conditional assignment turn the entire bus to X, which is very pessimistic, probably too much. Better would be to convert any Z bit to X, but leave the valid bits alone. That's the main change in this PR.
Also:
Fix some doc comments
Fix a missing link in CHANGELOG
Add some assertions to help catch SV generation issues in case users override built-in functionality from Logic, Module, etc.
Add a more interesting test on CustomSystemVerilog SV generation.
Related Issue(s)
N/A
Testing
Added new tests, plus existing tests cover a lot
Backwards-compatibility
Is this a breaking change that will not be backwards-compatible? If yes, how so?
No, but behavior will be slightly more optimistic now (closer to previous implementation).
Documentation
Does the change require any updates to documentation? If so, where? Are they included?
Description & Motivation
Previous changes made any invalid value on a conditional assignment turn the entire bus to
X, which is very pessimistic, probably too much. Better would be to convert anyZbit toX, but leave the valid bits alone. That's the main change in this PR.Also:
Logic,Module, etc.CustomSystemVerilogSV generation.Related Issue(s)
N/A
Testing
Added new tests, plus existing tests cover a lot
Backwards-compatibility
No, but behavior will be slightly more optimistic now (closer to previous implementation).
Documentation
No