In cases where a uniquified array element name (e.g. "ArrayX" element 0 would be "ArrayX_0" internally) collided with actual submodule port names (e.g. a non-array port named "ArrayX_0"), the SystemVerilog generated would misconnect the non-array-element port to an index of the array. This was because array element names were assumed to be port names if their parent was a port, which is a false assumption.
This PR fixes the bug for both inputs and outputs. It also adds more robust checking and assertions in the generation to catch any similar issue up-front.
Related Issue(s)
N/A
Testing
Added one new test, plus more assertions and safety in the implementation.
Backwards-compatibility
Is this a breaking change that will not be backwards-compatible? If yes, how so?
No
Documentation
Does the change require any updates to documentation? If so, where? Are they included?
Description & Motivation
In cases where a uniquified array element name (e.g. "ArrayX" element 0 would be "ArrayX_0" internally) collided with actual submodule port names (e.g. a non-array port named "ArrayX_0"), the SystemVerilog generated would misconnect the non-array-element port to an index of the array. This was because array element names were assumed to be port names if their parent was a port, which is a false assumption.
This PR fixes the bug for both inputs and outputs. It also adds more robust checking and assertions in the generation to catch any similar issue up-front.
Related Issue(s)
N/A
Testing
Added one new test, plus more assertions and safety in the implementation.
Backwards-compatibility
No
Documentation
No