Support for bidirectional wires (LogicNets) and in-out ports (inOuts).
Added LogicNet
Added inOut ports to Module
Added TriStateBuffer
Deprecated CustomSytemVerilog and replaced with similar but more flexible APIs for SystemVerilog. BREAKING: This also impacted InlineSystemVerilog and ExternalSystemVerilogModule, whose APIs have changed.
Improved naming of intermediate, structure, and array signals in various places to make debug easier.
BREAKING: increased minimum Dart SDK to 3.0.0
BREAKING: updated Interface.connectIO API for inOutTags
Fixed a bug where expressionlessInputs may not have been honored in non-inline custom SystemVerilog modules.
Fixed a bug where in some cases an xor between two LogicValues could cause an exception due to a false width mismatch.
Added better checking, error handling, and message when module hierarchy cannot be properly resolved (e.g. self-containing modules, modules within multiple hierarchies).
Breaking: Updated APIs for Synthesizer.synthesize and down the stack to use a Function to calculate the instance type of a module instead of a Map look-up table.
Added srcConnections API to Logic to make it easier to trace drivers of subtypes of Logic which contain multiple drivers.
Related Issue(s)
Fix #8
Fix #476
Fix #477
Testing
Extensive new tests added for new features and bug fixes.
Backwards-compatibility
Is this a breaking change that will not be backwards-compatible? If yes, how so?
Yes!
Breaking: ExternalSystemVerilogModule and InlineSystemVerilog now extend SystemVerilog instead of CustomSystemVerilog, meaning the instantiationVerilog API arguments have been modified.
Breaking: Increased minimum Dart SDK version to 3.0.0.
Breaking: Interface.connectIO has an additional optional named argument for inOutTags. Implementations of Interface which override connectIO will need to be updated.
Breaking: Updated APIs for Synthesizer.synthesize and down the stack to use a Function to calculate the instance type of a module instead of a Map look-up table.
Documentation
Does the change require any updates to documentation? If so, where? Are they included?
Description & Motivation
Support for bidirectional wires (
LogicNet
s) and in-out ports (inOut
s).LogicNet
inOut
ports toModule
TriStateBuffer
CustomSytemVerilog
and replaced with similar but more flexible APIs forSystemVerilog
. BREAKING: This also impactedInlineSystemVerilog
andExternalSystemVerilogModule
, whose APIs have changed.Interface.connectIO
API forinOutTags
expressionlessInputs
may not have been honored in non-inline custom SystemVerilog modules.xor
between twoLogicValue
s could cause an exception due to a false width mismatch.Synthesizer.synthesize
and down the stack to use aFunction
to calculate the instance type of a module instead of aMap
look-up table.srcConnections
API toLogic
to make it easier to trace drivers of subtypes ofLogic
which contain multiple drivers.Related Issue(s)
Fix #8 Fix #476 Fix #477
Testing
Extensive new tests added for new features and bug fixes.
Backwards-compatibility
Yes!
ExternalSystemVerilogModule
andInlineSystemVerilog
now extendSystemVerilog
instead ofCustomSystemVerilog
, meaning theinstantiationVerilog
API arguments have been modified.Interface.connectIO
has an additional optional named argument forinOutTags
. Implementations ofInterface
which overrideconnectIO
will need to be updated.Synthesizer.synthesize
and down the stack to use aFunction
to calculate the instance type of a module instead of aMap
look-up table.Documentation
Yes! Added to and updated user guide