Currently, Const is just a Logic that initializes itself with a specific value. Technically, the value could be changed later via a put directly on the Const or on another Logic which shares an underlying _Wire. This can be confusing for debug, and worse, could cause synthesized outputs (e.g. SystemVerilog) to have constant values which do not match the requested value at the time of Const creation.
Desired solution
Some ideas:
Have a way to flag/throw an exception when the value of a Const is attempted to be changed
Have a way to ensure synthesized outputs have the intended constant value
Motivation
Currently,
Constis just aLogicthat initializes itself with a specific value. Technically, the value could be changed later via aputdirectly on theConstor on anotherLogicwhich shares an underlying_Wire. This can be confusing for debug, and worse, could cause synthesized outputs (e.g. SystemVerilog) to have constant values which do not match the requested value at the time ofConstcreation.Desired solution
Some ideas:
Constis attempted to be changedAlternatives considered
No response
Additional details
Somewhat related to #429