Open mkorbel1 opened 2 months ago
VHDL is a popular alternative to SystemVerilog
The capability to generate VHDL in addition to SystemVerilog, as well as instantiate external VHDL modules instead of only SystemVerilog (including for cosimulation)
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Motivation
VHDL is a popular alternative to SystemVerilog
Desired solution
The capability to generate VHDL in addition to SystemVerilog, as well as instantiate external VHDL modules instead of only SystemVerilog (including for cosimulation)
Alternatives considered
No response
Additional details
No response