In certain scenarios, it is possible for internal signals to not be discovered during Module.build() when they are connected element-wise to LogicArrays and not otherwise connected to other signals or sub-modules. This should not cause any functional issues in simulation or generated SystemVerilog, but it can affect whether signals are present in the generated outputs or discoverable by querying the internalSignals API. Some tools that leverage ROHD care about these, which was how the bug was discovered.
Related Issue(s)
N/A
Testing
Added a new test, existing tests cover functionality
Backwards-compatibility
Is this a breaking change that will not be backwards-compatible? If yes, how so?
No
Documentation
Does the change require any updates to documentation? If so, where? Are they included?
Description & Motivation
In certain scenarios, it is possible for internal signals to not be discovered during
Module.build()when they are connected element-wise toLogicArrays and not otherwise connected to other signals or sub-modules. This should not cause any functional issues in simulation or generated SystemVerilog, but it can affect whether signals are present in the generated outputs or discoverable by querying theinternalSignalsAPI. Some tools that leverage ROHD care about these, which was how the bug was discovered.Related Issue(s)
N/A
Testing
Added a new test, existing tests cover functionality
Backwards-compatibility
No
Documentation
No