This is a bug fix for when parameter arguments in custom-generated SystemVerilog have provided parameter information (either instantiation or definition), but the list/map is empty (but non-null). It is illegal SystemVerilog syntax to generate something like #( ), but that's what was being generated. The fix is to look for null OR empty conditions.
Related Issue(s)
N/A
Testing
Added a new test that covers both instantiation and definition empty parameter scenarios.
Backwards-compatibility
Is this a breaking change that will not be backwards-compatible? If yes, how so?
No
Documentation
Does the change require any updates to documentation? If so, where? Are they included?
Description & Motivation
This is a bug fix for when parameter arguments in custom-generated SystemVerilog have provided parameter information (either instantiation or definition), but the list/map is empty (but non-null). It is illegal SystemVerilog syntax to generate something like
#( )
, but that's what was being generated. The fix is to look fornull
OR empty conditions.Related Issue(s)
N/A
Testing
Added a new test that covers both instantiation and definition empty parameter scenarios.
Backwards-compatibility
No
Documentation
No