search

intel / synce4l

GNU General Public License v2.0
22 stars 11 forks source link

support interface priority when running Clock Selection Algorithm (CSA) with same recv QL #17

Closed dungxpt96 closed 3 months ago

dungxpt96 commented 1 year ago

Hi,

When synce4l receives the same QL from 2 interfaces, it should choose the better one as the best-selected port, it maybe come from the priority of interfaces.

As Cisco describes: https://www.cisco.com/c/en/us/td/docs/iosxr/ncs5000/sysman/62x/b-system-management-cg-ncs5000-62x/b-system-management-cg-ncs5000-62x_chapter_01100.html

Configure priority of the frequency source on a controller or an interface by specifying a value in the range 1 (highest priority) to 254 (lowest priority). The default value is 100. The priority value set is used by the clock-selection algorithm to choose between two sources that have the same quality level (QL) and lower priority values are usually preferred.

RP/0/RP0/CPU0:router(config-if-freqsync)# priority 101

Can we support this feature?

mmichaliINTC commented 1 year ago

Hello,

thanks @dungxpt96 - great finding! Yes, we have this feature on our list. We are planning to introduce "local priority" to config file. Let's have this issue open till it is implemented.

BR, M^2

kubalewski commented 6 months ago

@dungxpt96 - Fixed in #44 , please verify on dev branch.