Issues with multiple SyncE inputs

When synce4l is configured to use two ports of E810E, receiving the same QL or different QLs, I'm seeing some odd and nondeterministic behavior in the input priority setting and connections to RCLKA and RCLKB.

When I start synce4l the configuration printed by ynl --dump get-pins looks like this:

 {'board-label': 'C827_0-RCLKA',
                     'prio': 0,
                     'state': 'connected'},
                     'prio': 4,
                     'state': 'connected'}],
 {'board-label': 'C827_0-RCLKB',
                     'prio': 0,
                     'state': 'selectable'},
                     'prio': 5,
                     'state': 'selectable'}],
...
  'parent-pin': [{'parent-id': 2, 'state': 'disconnected'},
                 {'parent-id': 3, 'state': 'connected'}],
  'parent-pin': [{'parent-id': 2, 'state': 'connected'},
                 {'parent-id': 3, 'state': 'disconnected'}],

The first port is connected to RCLKB and the second port to RCLKA, but the priority of RCLKA and RCLKB are the same even though the ports receive different QL.

When I bring the first port down by ip link set, I get:

 {'board-label': 'C827_0-RCLKA',
                     'prio': 0,
                     'state': 'connected'},
                     'prio': 4,
                     'state': 'connected'}],
 {'board-label': 'C827_0-RCLKB',
                     'prio': 0,
                     'state': 'selectable'},
                     'prio': 5,
                     'state': 'selectable'}],
...
  'parent-pin': [{'parent-id': 2, 'state': 'disconnected'},
                 {'parent-id': 3, 'state': 'disconnected'}],
  'parent-pin': [{'parent-id': 2, 'state': 'connected'},
                 {'parent-id': 3, 'state': 'connected'}],

Now the second port is connected to RCLKA and RCLKB, which have the same priority. That seems ok.

When I bring the first port up again, I get the some pin configuration:

 {'board-label': 'C827_0-RCLKA',
                     'prio': 0,
                     'state': 'connected'},
                     'prio': 4,
                     'state': 'connected'}],
 {'board-label': 'C827_0-RCLKB',
                     'prio': 0,
                     'state': 'selectable'},
                     'prio': 5,
                     'state': 'selectable'}],
...
  'parent-pin': [{'parent-id': 2, 'state': 'disconnected'},
                 {'parent-id': 3, 'state': 'disconnected'}],
  'parent-pin': [{'parent-id': 2, 'state': 'connected'},
                 {'parent-id': 3, 'state': 'connected'}],

I think it should reconnect the first port as it has a higher-priority QL.

It's not clear to me how this should actually work. Is there any advantage of connecting different ports to different clocks, so the DPLL can have multiple inputs and maybe reduce the time needed to switch between the RCLK inputs when one of them is disconnected, or is it better to connect only one port and leave the other port disconnected? I assume connecting one port to both clocks doesn't have any advantages.

intel / synce4l

Issues with multiple SyncE inputs #37

41 Fix merged.