intel / systemc-compiler

This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
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Parameter transfer during module instantiation #61

Closed songlinli0803 closed 1 year ago

songlinli0803 commented 1 year ago

Hello,

I define a parameter NUM in My_module : static const int NUM = 7;

And this parameter is for port : sc_in< sc_uint<NUM> > a{"a"};

Then i would like to initialize this parameter in module constructor like this: SC_CTOR(My_module ); My_module (const sc_module_name& name, int NUM): sc_module(name), NUM(NUM) {}

But it doesn't work, because of the error : error: 'const int My_module::NUM' is a static data member; it can only be initialized at its definition

I also tried to change the signal definition to sc_in<bool> a[NUM]; but can't work either.

Do you have some good advise for this parameter transfer need, pls?

mikhailmoiseev commented 1 year ago

Hello,

Static member cannot be initialized in class constructor as it is common for the class type instances. You can initialize NUM via template parameter defining multiple types:

template <int N> 
class A : public sc_module {
    static const int NUM = N;
    sc_vector<sc_in<bool>>   a{"a", NUM};  // better than sc_in<bool> a[NUM]
    ...
};
A<3> a1{"a1"};
A<5> a2{"a2"};   // A<3> and A<5> are different types

-Mikhail

songlinli0803 commented 1 year ago

Thanks Mikhail,

Your method works very well!

mikhailmoiseev commented 1 year ago

Hope you found static logarithm functions in: https://github.com/intel/systemc-compiler/blob/main/components/common/sctcommon/sct_static_log.h

songlinli0803 commented 1 year ago

It seems very useful, thanks a lot