export SystemVerilog modules to multiple files?

[pmerz1]

Is there a way for ICSC not to write all SystemVerilog modules to one file?

I think sometimes it would be more convenient to split the modules into several files to make them easier to read.

What do you think?

[mikhailmoiseev]

No, only one SV file is generated. From my expirience working with one file is more convinient, specially for designs with hundreds of mudules. What advantages of multiple files do you see?

There is also a problem with template modules and modules with constructor parameters -- that lead to different SV modules generated.

[pmerz1]

I do understand that handling one file is more convinient if you are generating SystemVerilog for a large set of modules.

I had the experience, that I had to track issues in the generated SystemVerilog modules. For tracing and verificating the behaviour I prefer having several files for several modules. Sometimes I got lost in the file with hundreds to thousands of lines.. So it's actually a personal preference.

My suggestion would be to use a flag that indexes if you want to have multiple files. Perhaps you could sort the files according to the SystemC modules and write all derived SystemVerilog modules in one file.

[mikhailmoiseev]

Do you think it is possible to write a script to split one SV file into multiple files by keywords module/endmodule? I could add a low priority ticket for that, but cannot promise to implement it soon.

[pmerz1]

I am using a short script doing this as a workaround.

And I have no problem if you create a low priority ticket for this.

[mikhailmoiseev]

Sounds good. Will update you when it is completed.