Closed mxu9 closed 2 months ago
According to PCIe Spec 6.1 Section 7.5.1.1.9, Header Layout identifies the layout of the second part of the predefined header. The bit location of Header Layout is 6:0. The bit 7 indicates if it is multi-function device.
According to PCIe Spec 6.1 Section 7.5.1.1.9, Header Layout identifies the layout of the second part of the predefined header. The bit location of Header Layout is 6:0. The bit 7 indicates if it is multi-function device.