For EVEX there are some constraints documented for GATHER instructions:
If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault
The old Xeon Phi / KNC documentation does not mention such constraints for MVEXGATHER instructions. However, usually the MVEX instructions behave very close to their EVEX counterparts. We are wondering, if the same constraint applies to MVEX instructions as well and is just not properly documented yet.
The KNC GATHER instructions forbid using the same vector register for destination and for the index.
I'm not sure if this will end up with #GP fault or #UD fault.
Hi there,
sorry to bother you with KNC stuff again 😋
For
EVEX
there are some constraints documented forGATHER
instructions:The old Xeon Phi / KNC documentation does not mention such constraints for
MVEX
GATHER
instructions. However, usually theMVEX
instructions behave very close to theirEVEX
counterparts. We are wondering, if the same constraint applies toMVEX
instructions as well and is just not properly documented yet.Do you know something about that?
Best, Florian