arm-nacl-gcc emits invalid nacl binary for 64bit left shift

[GoogleCodeExporter]

Platform (e.g. "pepper_14"): native_client HEAD
Toolchain variant (e.g. "newlib" or "glibc"): linux_arm_newlib

What steps will reproduce the problem?

1. Save the following as ll_shift.c

int _start() {
  unsigned long long a = 999;
  int b = 3;
  a <<= b;
}

2. ~/src/nacl/native_client/toolchain/linux_arm_newlib/bin/arm-nacl-gcc 
ll_shift.c -mfpu=neon -nostdlib

3. ncval_arm a.out
   2003c: Load/store base r3 is not properly masked.
Invalid.

What is the expected output?

The validation should pass.

What do you see instead?

The validation failed.

Please provide any additional information below.

Looks like we can workaround this issue by just disabling neon for 64bit shift, 
but this might not be a good fix.

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 5f1a747..f8342e3 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -3499,7 +3499,7 @@
                    (match_operand:SI 2 "general_operand" "")))]
   "TARGET_32BIT"
   "
-  if (TARGET_NEON)
+  if (TARGET_NEON && 0)
     {
       /* Delay the decision whether to use NEON or core-regs until
     register allocation.  */
@@ -3587,7 +3587,7 @@
                      (match_operand:SI 2 "reg_or_int_operand" "")))]
   "TARGET_32BIT"
   "
-  if (TARGET_NEON)
+  if (TARGET_NEON && 0)
     {
       /* Delay the decision whether to use NEON or core-regs until
     register allocation.  */

Original issue reported on code.google.com by ham...@chromium.org on 29 Jun 2013 at 9:42

[GoogleCodeExporter]

Moved to issue nativeclient:3543.

Original comment by mseaborn@chromium.org on 3 Jul 2013 at 3:46

• Changed state: Duplicate