Add Xilinx ICAP/IPROG interfaces

[jhegeman]

This pull request introduces Xilinx ICAP and IPROG interfaces for IPbus. Both interfaces exist for 7-series as well as for UltraScale(+). The corresponding Xilinx examples have been expanded to demonstrate these interfaces.

Two new entities are available:

• ipbus_icap_x7/ipbus_icap_usp An interface to the Xilinx ICAP primitive, with support for register reads and writes, as well as for FPGA reconfiguration from a configurable base address.
• ipbus_iprog_x7/ipbus_iprog_usp An interface to the Xilinx ICAP primitive, with only support for FPGA reconfiguration (from a configurable base address).

The README file in the projects/xilinx directory has been updated with instructions to run the new demonstration scripts as well.

[tswilliams]

Hi Jeroen,

Thanks for opening this pull request! I haven't used the ICAP & IPROG directly before, so I'm still reading through the documentation to gain a better understanding of the use cases, but it seems like IPbus access to them will be very useful.

One small comment so far: The ICAP primitive name is the same for Ultrascale and Ultrascale+ devices, correct? If so, then for consistency with the name of the DNA IPbus slave (ipbus_device_dna_us_usp), we should rename ipbus_icap_usp.{dep,vhd} to ipbus_icap_us_usp.{dep,vhd}, and ipbus_iprog_usp.{dep,vhd} to ipbus_iprog_us_usp.{dep,vhd}, right?

Cheers, Tom

[jhegeman]

Hi Tom,

Yes, you are correct about the naming (and about the US and USP ICAP primitives being the same). I have updated the names, and rechecked that everything still synthesises.

The main use case for this, in our context, is I'd say the possibility to dynamically reconfigure the FPGA from an image at an arbitrary address, as well as the access to several of the under-the-hood registers (like BOOTST).

The IPROG slave is just a reduced version of the ICAP slave. In case people only want/need the reconfiguration functionality.

Cheers, Jeroen

[tswilliams]

Run tests, please

[tswilliams]

Hi,

Thanks for renaming the slaves. When taking a look at the VHDL, I couldn't spot components/ipbus_util/firmware/hdl/icap_us_usp.vhd being used anywhere (either in depfiles, or in other VHDL files). Did I miss something, or is this an early implementation of some of the ICAP slave logic, which can now be removed?

Cheers, Tom

[jhegeman]

Yeah, that was my prototype. I actually found that again while renaming but then forgot to remove it. Will fix that.

[jhegeman]

Hi @tswilliams,

Sorted now. No more left-overs left, I believe.

Cheers, Jeroen