Closed jhegeman closed 4 years ago
Just a tiny patch to make all port assignments obey true VHDL syntax in order to avoid Vivado producing 'critical warnings.'
Run tests, please
Crap. I actually an Vivado's syntax check on this, but not synthesis... I guess I can't truly multi-task after all.
Anyway... Should be fixed now. (For both signals.)
Just a tiny patch to make all port assignments obey true VHDL syntax in order to avoid Vivado producing 'critical warnings.'