Use generics to specify PCI identifiers (instead of hard-coding them)

[jhegeman]

Hi,

Just a simple change, really. This makes the various PCI identifiers accessible as generics in the pcie_xdmaaxi* interfaces.

This should avoid users copying the whole XDMA IP core just to customise these identifiers.

Best regards, Jeroen

[tswilliams]

Hi,

Thanks for this. Did you change the .xci files as well? When I tried this branch out with a Serenity build, I get the following errors in synthesis:

synth | ERROR: [Synth 8-3493] module 'xdma_0' declared at './.Xil/Vivado-31993-heplnw017.pp.rl.ac.uk/realtime/xdma_0_stub.vhdl:5' does not have matching formal port for component port 'cfg_subsys_vend_id' [/data/tsw/firmware/tmp/ipbus-pull204-test/src/ipbus-firmware/components/ipbus_pcie/firmware/hdl/pcie_xdma_axi_us_if.vhd:156]
synth | ERROR: [Synth 8-3493] module 'xdma_0' declared at './.Xil/Vivado-31993-heplnw017.pp.rl.ac.uk/realtime/xdma_0_stub.vhdl:5' does not have matching formal port for component port 'cfg_vend_id' [/data/tsw/firmware/tmp/ipbus-pull204-test/src/ipbus-firmware/components/ipbus_pcie/firmware/hdl/pcie_xdma_axi_us_if.vhd:156]
synth | ERROR: [Synth 8-3493] module 'xdma_0' declared at './.Xil/Vivado-31993-heplnw017.pp.rl.ac.uk/realtime/xdma_0_stub.vhdl:5' does not have matching formal port for component port 'cfg_dev_id_pf0' [/data/tsw/firmware/tmp/ipbus-pull204-test/src/ipbus-firmware/components/ipbus_pcie/firmware/hdl/pcie_xdma_axi_us_if.vhd:156]
synth | ERROR: [Synth 8-3493] module 'xdma_0' declared at './.Xil/Vivado-31993-heplnw017.pp.rl.ac.uk/realtime/xdma_0_stub.vhdl:5' does not have matching formal port for component port 'cfg_rev_id_pf0' [/data/tsw/firmware/tmp/ipbus-pull204-test/src/ipbus-firmware/components/ipbus_pcie/firmware/hdl/pcie_xdma_axi_us_if.vhd:156]
synth | ERROR: [Synth 8-3493] module 'xdma_0' declared at './.Xil/Vivado-31993-heplnw017.pp.rl.ac.uk/realtime/xdma_0_stub.vhdl:5' does not have matching formal port for component port 'cfg_subsys_id_pf0' [/data/tsw/firmware/tmp/ipbus-pull204-test/src/ipbus-firmware/components/ipbus_pcie/firmware/hdl/pcie_xdma_axi_us_if.vhd:156]
synth | ERROR: [Synth 8-285] failed synthesizing module 'pcie_xdma_axi_us_if' [/data/tsw/firmware/tmp/ipbus-pull204-test/src/ipbus-firmware/components/ipbus_pcie/firmware/hdl/pcie_xdma_axi_us_if.vhd:47]

I don't see any changes to the XCI files in this branch, but I assume they need to be updated in order to activate the ports mentioned in these errors messages.

Cheers, Tom

[jhegeman]

Hi Tom,

I keep forgetting that source files are linked, whereas core files are copied. So the modified .xci files did not make it into the commit. I have updated the core files now.

By the way:

• All xdma_0 .xci files are now created with Vivado 2019.1.3. (Before they were a bit of a mix.)
• Is it intentional that the US and US-bypass cores have a different PCI device ID from the USP one?

Cheers, Jeroen

[tswilliams]

Thanks - also for updating the XCI files to the same Vivado version at the same time.

Regarding the different PCI devices IDs, I thought that these values were the defaults from Xilinx - i.e. 9031 for Ultrascale+ and 8031 for Ultrascale. That said, if that doesn't match what you've seen before with Vivado, let me know - it could be this is in fact a difference that we made in the files during development a few years ago and didn't notice at the time.

Cheers, Tom

[jhegeman]

You could very well be correct about these device IDs. I just noticed that they were different and was not sure what to expect. Let's not touch them for the moment, then.

Jeroen

[tswilliams]

Run tests

[tswilliams]

@jhegeman - OK, thanks again for this change. I've just tested on a couple of Serenity daugther cards, and everything worked as expected, so I'll merge in the branch as soon as the CI completes.