I noticed that the top_k800_xdmaBypass example project does not build due to a signal width mismatch.
Vivado tells me:
ERROR: [Synth 8-549] port width mismatch for port 'axi_ms[araddr]': port width = 16, actual width = 64
[/afs/cern.ch/work/j/jhegeman/cms_tcds2/contrib_ipbus/bypass_check/src/ipbus-firmware/boards/k800/synth/firmware/hdl/k800_infra.vhd:158]
ERROR: [Synth 8-549] port width mismatch for port 'axi_ms[awaddr]': port width = 16, actual width = 64
[/afs/cern.ch/work/j/jhegeman/cms_tcds2/contrib_ipbus/bypass_check/src/ipbus-firmware/boards/k800/synth/firmware/hdl/k800_infra.vhd:158]
ERROR: [Synth 8-285] failed synthesizing module 'k800_infra'
[/afs/cern.ch/work/j/jhegeman/cms_tcds2/contrib_ipbus/bypass_check/src/ipbus-firmware/boards/k800/synth/firmware/hdl/k800_infra.vhd:80]
ERROR: [Synth 8-285] failed synthesizing module 'top'
[/afs/cern.ch/work/j/jhegeman/cms_tcds2/contrib_ipbus/bypass_check/src/ipbus-firmware/boards/k800/synth/firmware/hdl/top_k800.vhd:67]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
Hi,
I noticed that the top_k800_xdmaBypass example project does not build due to a signal width mismatch.
Vivado tells me:
This happens here: https://github.com/ipbus/ipbus-firmware/blob/master/boards/k800/synth/firmware/hdl/k800_infra.vhd#L158 because the XDMA-bypass results in a 16-bit axi_ms signal, whereas the 'real' version results in a 64-bit wide axi_ms. (In terms of araddr and awaddr, that is.)
Cheers, Jeroen