Fix the oscillator clock frequency in the VCU118 SGMII infrastructure

[jhegeman]

The frequency of the VCO clock frequency in the VCU118 SGMII infrastructure is incorrect. This leads to complaints from Vivado about: [DRC AVAL-168] MMCM_ADV Phase shift and divide attr checks: The MMCME4_ADV cell infra/clocks/mmcm has a fractional CLKFBOUT_MULT_F value (3.333) which is not a multiple of the hardware granularity (0.125) and will be adjusted to the nearest supportable value. Please update the design to use a valid value.

This patch fixes that by correcting the MMCME4 generic values provided in the infrastructure code.

The above can be easily reproduced (using Vivado 2021.2) by building the top_vcu118_sgmii.dep example.

[thasti]

I confirm that I have seen this same issue (on Vivado 2022.2). My fix was to change the aux frequency instead (which is not used in the example design anyways):

    clocks : entity work.clocks_usp_serdes
        generic map (
            CLK_FR_FREQ => 300.0,
            CLK_VCO_FREQ => 1500.0,
            CLK_AUX_FREQ => 50.0
            )

[tswilliams]

Run tests, please