Open DavidMonk00 opened 7 months ago
In VHDL-2019 (and supported in Vivado 2023.2), there is the ability to bundle entity signals into a single line of code.
Implementing this for ipbus components would significantly reduce code verbosity and simplify designs.
In VHDL-2019 (and supported in Vivado 2023.2), there is the ability to bundle entity signals into a single line of code.
Implementing this for ipbus components would significantly reduce code verbosity and simplify designs.