Add clk200 as a port to enclustra_ax3_pm3_infra.vhd

ipbus / ipbus-firmware

Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol

https://ipbus.web.cern.ch

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Open DavidCussans opened 6 years ago

DavidCussans commented 6 years ago

It would be useful it the 200MHz clock generated inside enclustra_ax3_pm3_infra.vhd was connected as a top-level port.

A 200MHz clock is needed to as an input to the Input delay calibration block.

boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/enclustra_ax3_pm3_infra.vhd

alessandrothea commented 5 years ago

Hi David, is this still needed?