Add d7 clock divider output for ~2 MHz clock synthesis for MDIO/MDC

[gpetruc]

Add one more clock divider output to ipbus_clock_div that will produce a ~2 MHz clock when starting from the usual 125 MHz input. This is needed for configuring the external ethernet PHY device of the Xilinx VCU118 boad using the MDIO/MDC control lines, and can be useful for any other external ethernet device (the specifications of the protocol require the clock frequency to be less than 2.5 MHz). This change adds no logic at all, so I think it should be completely transparent in any design where the new input is not used.

[ipbus-bot]

Can one of the admins verify this patch?

[alessandrothea]

ok to test (again)

[alessandrothea]

run tests, please

[alessandrothea]

Superseded by #120