PCIe-based interface for IPbus transactor

Over the past couple of years, we've developed firmware entities that allow one to read & write lists of IPbus transactions over PCIe - i.e. a PCIe transport layer interface for the IPbus transactor. These have been working reliably for a long time, and from my perspective are ready for inclusion in a release.

The current solution makes use of the Xilinx PCIe DMA (aka XDMA) IP core - and associated Linux driver - to convey the lists of transactions over the the PCIe link. This IP core presents an AXI4 bus, which is then connected to an AXI4 BRAM controller IP core. A newly-written VHDL entity - ipbus_transport_ram_if - is connected to the corresponding BRAM interface; this entity accumulates lists of transaction requests in BRAMs as they are written, presents them to the IPbus transactor when they are ready, and stores the resulting replies in BRAMs that can be read later over the PCIe link through the top-level ports of ipbus_transport_ram_if.

The detailed CPU-FPGA interface is as follows:

Address space is separated into N pages, with 1 IPbus packet per page (same internal packet format as with IPbus 2.0 over UDP/TCP); i.e. N = maximum number of packets in flight
FPGA-to-CPU (in 32-bit words)
- Word 0: N
- Word 1: M = number of 32-bit words per page
- Word 2: Index of next request (CPU-to-FPGA) page to fill
- Word 3: Number of reply pages that have been filled
- For i in 0 to N-1:
  - Word 4 + M * i : Start of page i ; value is 0x00010000 + number of words in IPbus reply packet excluding packet header
  - Words 5 + M * i to 5 + M * i + packet size: IPbus reply packet
CPU-to-FPGA (in 32-bit words)
- For i in 0 to N-1:
  - Word M * i : Start of page i; value is 0x00010000 + number of words in IPbus request packet excluding packet header
  - Word M * i + 1 to M * i + 1 + packet size : IPbus request packet

ipbus / ipbus-firmware

PCIe-based interface for IPbus transactor #95