Layout versus schematic (LVS)

[joamatab]

As circuits become more complex is important to check that your design intent matches the produced layout

What are your plans for LVS?

We just added schematic driven layout in gdsfactory and netlist extraction and we were wondering the best way to compare both. See issue

i was wondering if this is something that you also plan on implementing in KQCircuits

[caspar-iqm]

Hi! I agree that LVS verification is very important!

In KQCircuits we have netlist extraction implemented, and it runs by default during the mask export stage. For each chip, a netlist in JSON format is extracted. It contains the following information:

• All elements on the chip, and the parameters that were used for each element
• The connections between elements

The netlist connectivity is based on ports that are defined in each element. Here, waveguides are also considered elements, since for a typical QPU design we work at microwave frequency and they cannot be considered simply "wires".

For processing the netlist data we have still fairly limited support:

• Functions to load and plot a connectivity graph of the netlist, see API documentation
• A command-line python script netlist_as_graph to load a json file and draw the graph on screen or save as PNG.