Open nirvedhmeshram opened 1 month ago
Failure is seen in following tests LLVMCPU/test/pipeline_pad_tests.mlir An example of IR from pipeline_tile_and_fuse.mlir is here https://gist.github.com/nirvedhmeshram/3349f2739dfb529fa4800040bf1c8490 It needs to be verified that the IR generated is what we want and then the CHECK's need to be updated, the reason for this change is this PR https://github.com/llvm/llvm-project/pull/108032
pipeline_tile_and_fuse.mlir
@Groverkss this is not urgent, so whenever you have cycles could you please take a look.
I'll take a look when I have cycles. The pipeline is really not used at all, so it is on low priorities.
Failure is seen in following tests LLVMCPU/test/pipeline_pad_tests.mlir An example of IR from
pipeline_tile_and_fuse.mlir
is here https://gist.github.com/nirvedhmeshram/3349f2739dfb529fa4800040bf1c8490 It needs to be verified that the IR generated is what we want and then the CHECK's need to be updated, the reason for this change is this PR https://github.com/llvm/llvm-project/pull/108032