For the sake of science...

[PJVol]

Hi! Just took a look into your acpimmio module, and wanted to ask How did you know the bitmask for the cg1pll_fcw0_frac_override (CG1PLL_FBDIV_Fraction in old docs) ? ) In the docs I have it's either missing or incorrect.

[irusanov]

Asus tool that could set bclk, r/w everything to observe changes and some trial and error. It doesn't work correctly on Raphael though. IIRC adjusted those masks 2-3 times before I got it correctly. At the time I also had discussions with other people, so we figured it out together, thus you can say I got some additional help.

[PJVol]

Nice, and yeah, Asrock has the utility "A-Tuning", allowing to set bclk on-the-fly. I was curious though, since my board has no external CG, if you're still able to control PLL fcw0 in this case... Is CG1 just work as the clock reciever this way, I mean if external clock came from GPP3 pins?

IIRC adjusted those masks 2-3 times before I got it correctly

You mean you have to do that constantly or it's about finding out the correct mask for Zen4?

[irusanov]

It was mostly intended for the internal CPU PLL on boards without external one and the mobile machines, although the range is very limited. I'm not sure it will work in every case, perhaps it depeds how the board is configured (in the case when using external CG). For example, my current board (X670E Gene) has sync and async mode. In async mode it probably uses 2 different CG registers, but I haven't really looked into it yet.

My bad about Raphael, it is not working correctly on the 6800HS I have. It still sets it, but the masks (and/or fraction multiplicator) are probably different as the set BCLK is different than the intended one and the one that is calculated/read back.

[PJVol]

My bad about Raphael, it is not working correctly on the 6800HS I have. It still sets it, but the masks (and/or fraction multiplicator) are probably different as the set BCLK is different than the intended one and the one that is calculated/read back.

I see... you meant Zen3+ not Zen4. Well, apparently APU in this regard is still a thing-in-itself

Btw, do you know any way to setup VDDCR_SOC rail voltage? Asrock just hide the whole "external voltages" menu partition from BIOS if 5800X3D is installed (their "died X3Ds from wrong Vsoc" panic mode), so that I have to use modified BIOS user profile to get the SOC voltage control back at least

[irusanov]

You can try the ACPI BIOS function if there's one exposed. The SMU command for setting VSOC VID on the fly was blocked/removed a long time ago, unfortunately. You would need to restart and hopefully that setting sticks, even when hidden from the setup menu. This should set it as it is entered in the AMD Oveclock menu.

[PJVol]

I've tried ACPI commands from a console (no luck). Nice to see you have updated SDT ) I'll give it a try. Thanks!

[PJVol]

Don't know why it didn't work from console, but it does work from your tool. Some thoughts:

1. There's ambiguous reference to "Formatting" in SettingsForm.cs (line 616) - solved it with Formatting = Newtonsoft.Json.Formatting.Indented
2. I had to remove and add again Assembly reference to Newtonsoft.Json to successfully build.
3. The only thing's left is to figure out how to set LL slope and Offset trims. They are encoded by 22:24 and 25:26 bits of SVD packet respectively

[irusanov]

Doesn't cause issues for me, the package is included at the top and the enum is correctly referenced. Not that what you did is wrong though, but there must be some difference between mine and your environment. Also it is 815 line for me.

Do you enter a VID or direct value? Zen4 bioses now have it in mV, but I haven't tried yet as I have full control with 7950X.

As for the LLC, I have no clue :/

PS: The app code is a mess, but my highest priority is the DLL.

[PJVol]

Strange, but I have an extra line (13) "using System.XML" that seems to lead to abmbiguous reference. Honestly, got no idea where it cаme from, lol, and yeah, this line # is 816 (#815 without the above line) I entered VID in decimal and was right on the 1st guess.

Zen 2-3 bioses have it in mV or V either way. Though there's only one section where 8bit VIDs are accepted, and to which ACPI command actually does write Vsoc value - it's missing on my Asrock board but it can be found on my MSI B450

[PJVol]

Thanks!

[irusanov]

I have just tried with a 240GE running on B550 Unify-X and the vsoc didn't change, it seems to be using an auto-rule and all oveclocking features are not availvable in bios - voltages, P-States, VSOC VID, etc.

SMT EN command works though, I've used it in the past. Perhaps the downcore control would work as well.

[PJVol]

I have just tried with a 240GE running on B550 Unify-X and the vsoc didn't change, it seems to be using an auto-rule and all oveclocking features are not availvable in bios - voltages, P-States, VSOC VID, etc.

Did you enter Vsoc as SVI2 VID? It seems the only accepted encoding for this command's argument. Anyway, what I was talking about initially is to figure out the way to control VRM directly, as the Asrock and other vendor's utilities do, changing controller settings runtime without the need to reboot. I believe they using SMBUS or I2C driver calls to access PWM controller registers, because it's the only way to set real voltages and offsets, PWM frequency, etc. Although, the load-line settings exposed in a BIOS seem to be accessible via SVI2, at least there are corresponding bitfields in a SMU::SMUIO::SMUSVI0_PLANE0_LOAD and SMU::SMUIO::SMUSVI0_PLANE1_LOAD registers mapped to the SMN address space. The problem is these fields are readonly for IPs with trust level > 2, i.e. for anything other than MP0, MP1, uCode, RSMU

[irusanov]

Yes, it just doesn't change at all, but this APU is not really overclockable. To overclock it, I use a potential bug in PStates where DID = 2 allows me to go beyond stock boost, while the default 4 doesn't. It seems to be the only way at least on that board.

I see now what you mean about the LLC. Unfortunately I don't know a way to control them through the SMN mailboxes. You would need SMBUS/I2C and the documentation for the chip. On my asrock B350 I could asjust it with the help of elmor's EVC2 tool by connecting the SDA and SCL pins to the PWM IC directly, but the tool had support for it. Maybe look into other popular tools if they have some support. Which IC do you have? Maybe EVC2 has it already.

You can download the software here and see if there's a file for your controller in the I2C_DEVICES folder: https://onedrive.live.com/?authkey=%21AKa7PP9wasztCqs&id=FABF1EAAEEBFA9D9%211585306&cid=FABF1EAAEEBFA9D9&parId=root&parQt=sharedby&parCid=B4D04F8925204E5B&o=OneUp

[PJVol]

It's RAA 229004 (or ISL 69138) for the VDD_CPU and VDD_SOC uP1674 for VDIMM NCT3933U for VDDP, VTT_DDR and 1P8V There is a file 69138_test.xml in configs folder

All voltages, including CPU rails controlled via NCT6796D smbus master