Additional output formats

[Muxianesty]

Currently SystemVerilog modules are the only artifacts being produced with Utopia HLS. Additional output formats should be considered:

• Unscheduled DFCIR
• Scheduled FIRRTL
• VHDL (?)
• Verilog (?)
• .dot (?)

[ssmolov]

I'd rather split different formats into different issues.

For now, DFCIR/FIRRTL are the most preferable ones, DOT is also can be helpful for self-debugging.

Concerning Verilog, it should be checked carefully. We can already generated it but treat as SystemVerilog because of predefined ".sv" extension of the output file.

As for VHDL, I'd recommend to look for MLIR/CIRCT extensions that are capable to provide it.

[Muxianesty]

I'd rather split different formats into different issues.

For now, DFCIR/FIRRTL are the most preferable ones, DOT is also can be helpful for self-debugging.

Concerning Verilog, it should be checked carefully. We can already generated it but treat as SystemVerilog because of predefined ".sv" extension of the output file.

As for VHDL, I'd recommend to look for MLIR/CIRCT extensions that are capable to provide it.

I agree with the proposal to make different issues for different formats. About .sv - as far as I understand, the output extension is not hardcoded and you can choose any valid Unix path to a file with any valid extension.