optiboot can start sketchs with inconsistent regster configuration side-effects

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What steps will reproduce the problem?
1. Send serial traffic during or immediately after reset
2.
3.

What is the expected output? What do you see instead?
In most cases (simple timeout, "Go" command), optiboot causes the sketch to 
start by allowing a watchdog timeout to occur, and then immediately running the 
sketch (having noticed that it was a WDT or powerup that reset the chip.)  Thus 
the sketch is started with the AVR in its "reset" configuration of all IO 
registers/etc.  However in the verifySpace() function appstart() is called 
directly, which means that if serial data (that is NOT valid bootloader 
traffic) is received after a reset, the sketch could be started with the timer 
and uart still configured with the bootloader settings.  (other cases where 
this could happen were fixed previously.)

What version of the product are you using? On what operating system?
This is with the latest mercurial source distribution.

Please provide any additional information below.
found by code inspection; I don't know if this has caused visible problems.
This is also http://code.google.com/p/optiboot/issues/detail?id=37

Original issue reported on code.google.com by wes...@gmail.com on 21 Apr 2011 at 10:52

Attachments:

• vs.diff

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Original comment by wes...@gmail.com on 5 Jun 2011 at 7:19

• Added labels: Component-optiboot

[GoogleCodeExporter]

Original comment by wes...@gmail.com on 11 Jun 2011 at 6:05

• Changed state: Started

[GoogleCodeExporter]

Fixed in the 1.0-associated sources, and now shipping on new hardware.

Original comment by wes...@gmail.com on 20 Dec 2011 at 6:33

• Changed state: Fixed