SystemVerilog support

[krupan]

Would it be possible to get SystemVerilog support? I noticed that in the VHDL issue (#203) a repository of sample code for VHDL and SystemVerilog was supplied: https://github.com/mbgh/aes128-hdl

[jacktasia]

Would it be possible to get SystemVerilog support?

Almost certainly. I'll look into this after work tonight.

Thanks for opening this!

[jacktasia]

@krupan I've added basic SystemVerilog support to dumb-jump. The update is now available via MELPA too. Please let me know if you have any feedback. Thanks!

[krupan]

Some quick stream of consciousness observations:

It's kinda sorta working :-) It often presents me with a long list (5 to 10) of choices when I do a dumb-jump-go, but the definition is usually in the list. Sometimes the list is too long for me to want to search through (20ish?). For some things it doesn't offer any choices and it just jumps to the wrong place. It's a tough language. I know none of this is going to help you without code examples...Maybe tonight outside of my day job responsibilities I can get you some code examples.

Seems to do functions quite well. I'm noticing that it doesn't seem to handle tasks (which are like functions). That would be nice. Hmm, looks like it doesn't do int's either. There are a lot of types in SystemVerilog. Here are some of them:

https://www.doulos.com/knowhow/sysverilog/tutorial/datatypes/

It doesn't seem to handle this:

class some_class extends some_other_class;

It can't find the definition of some_other_class. Simple class instances like this:

some_class some_class_instance;

It can jump to the definition of some_class. That's nice. It can't jump to the above line when I run dumb-jump-go on another use of some_class_instance (gives me a too long list).

OK, I better get back to work. Not a bad start!

[jacktasia]

@krupan Thanks for the feedback. It's definitely a more complex language than I had thought. I was basing it almost purely off https://github.com/mbgh/aes128-hdl. I've made a few small improvements in #220 based on what you've said here that should be in MELPA now.

Do you know of any open source SystemVerilog repo(s) that have good examples of what dumb-jump still needs to support? Thanks again.

[krupan]

You are awesome. We SystemVerilog users rarely get any support from open source tools.

The UVM is a big bundle of open source SystemVerilog code that almost all SystemVerilog developers use:

http://www.accellera.org/images/downloads/standards/uvm/uvm-1.2.tar.gz

It's a bit of a beast and uses lots of language features that the AES core does not.

I'll update my dumb-jump package and try out your new changes as soon as I get a chance.

[jacktasia]

Thanks for the link! I'll take a look at the code and see what else I can add. Please let me know if you have any more feedback.

[krupan]

I'm trying the latest version. Here's a specific issue. First file:

class foo;
    some_package::some_class some_class_inst;
endclass

In another file:

package some_package;
`include "some_class.sv"
endpackage

Inside some_class.sv:

class some_class;
    //class stuff
end class

When I run dumb-jump-go on the first file, it jumps straight to the `include in the second file. It should jump to the third file (some_class.sv).

[jacktasia]

@krupan Thanks for the report! I will take a look at this after work today and get this fixed. I'll also try to add some more improvements from the example library you provided. I really appreciate the feedback so I can make dumb-jump better for everyone. Thanks again.

[jacktasia]

@krupan I tried to reproduce your some_class example above, but I have been unable to so far. It seems to be working as expected for me.

If you could please try in debug mode and report back the output that would be great: http://p.cweiske.de/506

if you could also compare it to the bare example gist/repo I made from your report: https://gist.github.com/jacktasia/2ae5fd25cd702ff8718fb4139bf9dbd3

You can clone the example this like:

git clone https://gist.github.com/2ae5fd25cd702ff8718fb4139bf9dbd3.git sv sv-test

then probably emacs sv-test/f1.sv

I am very curious to see if you get different behavior there too. Thanks so much for all your help!