Can't find axisfifo under the /dev

[markusxu]

I tried to use AXI_Stream_FIFO v4.2 IP core in Petalinux. I enabled the Xilinx AXI-Stream FIFO v4.1/v4.2 IP core driver directly in the petalinux kernel configuration, but after booting I did not find a device like /dev/axis_fifo__########. I'd like to ask what's going on, is there an operation I'm missing?

Board: ZCU104 Petalinux Version: 2020.2 Vivado Version: 2020.2

dmesg: dmesg.txt

pl.dtsi: pl.dtsi.txt

vivado bd: top_design.pdf

[jacobfeder]

Usually this is a due to not connecting the IP block correctly in the block diagram. Make sure you have the interrupt lines connected.

[jacobfeder]

https://github.com/jacobfeder/axisfifo/issues/2

[markusxu]

I checked all my connections and it's now stuck at

[ 17.183168] axis-fifo driver loaded with parameters read_timeout = 1000, write_timeout = 1000

There is no output after this log

[jacobfeder]

Does the device show under /dev/axisfifo######## ? If so, try reading/writing it.

[esorton]

Should see something similar to below in the kernel output if the devices are detected:

axis_fifo 43c00000.axi_fifo_mm_s: axis-fifo created at 0x43c00000 mapped to 0x0xf0910000, irq=49, major=244, minor=0
axis_fifo 44040000.axi_fifo_mm_s: axis-fifo created at 0x44040000 mapped to 0x0xf0930000, irq=53, major=243, minor=0

Just grabbed this off one of my test systems built with 2020.1 and an older version of axisfifo.

Can anyone confirm success with 2020.2? I have never had an issue with axisfifo when the version upgraded, but I have had problems in other subsystems.

[jacobfeder]

I'm guessing you already checked for IP version update? https://github.com/jacobfeder/axisfifo/issues/3

[markusxu]

No, in fact I can't even get into Linux. By the way, I'm using version 2020.2, is there a version problem

[gutelfuldead]

I checked all my connections and it's now stuck at

[ 17.183168] axis-fifo driver loaded with parameters read_timeout = 1000, write_timeout = 1000

There is no output after this log

If Linux freezes here it could because the AXI Clock isn't connected (or not enabled in the dts) and the module probe locks up when it tries to access the FPGA register via AXI4-Lite. I would make sure,

1. aclk and aresetn are connected correctly
2. fclk is enabled in device tree
3. you have the correct address for the logic in the dts entry

I've only tested on 2018.2 but I'd be surprised if this was caused by a version issue.

[markusxu]

If Linux freezes here it could because the AXI Clock isn't connected (or not enabled in the dts) and the module probe locks up when it tries to access the FPGA register via AXI4-Lite. I would make sure,

1. aclk and aresetn are connected correctly
2. fclk is enabled in device tree
3. you have the correct address for the logic in the dts entry

I've only tested on 2018.2 but I'd be surprised if this was caused by a version issue.

As you say, I do have a problem with the AXI clock, but not in any of the cases you listed.

In my original design AXI_Stream_FIFO uses an AXI clock frequency that is less than the PS to PL AXI clock frequency, and uses AXl lnterconnect to convert between them.

I created a new test project to get the two speeds to be the same and the driver worked. At startup the following message is printed:

[   16.937270] axis-fifo driver loaded with parameters read_timeout = 1000, write_timeout = 1000
[   16.948309] axis_fifo a0000000.axi_fifo_mm_s: axis-fifo created at 0x00000000a0000000 mapped to 0x0xffff800011440000, irq=48, major=242, minor=0

But I also want to know how I can change the clock frequency of the AXI and still be able to run it properly!

@gutelfuldead Thank you very much if you can answer!

[markusxu]

I made a mistake and indeed there was no signal from the AXI clock.

[hemanthr28]

Hello, I am facing the same issue with my design. I have connected all the clocks and resets as required. When I load the module, the probe function is not called. I have tried adding printk's to verify this (none of the printk's in the probe function is executed). I only have the below output. I am using Petalinux 2020.2 and Vivado 2020.2. dmesg output - [ 104.140093] axis_fifo: loading out-of-tree module taints kernel. [ 104.147218] axis-fifo driver loaded with parameters read_timeout = 1000, write_timeout = 1000

I have attached the design for reference, any help would be appreciated. Thank you. zynq_ps.pdf

[jacobfeder]

I'm pretty rusty on this, but iirc you need some sort of interrupt multiplexing block rather than putting it directly into the PS block? It could also be different with ultrascale devices compared to what I was using.

[hemanthr28]

Thank you for your quick reply. I will try to use a similar approach and see if it works.