Closed b-s-a closed 2 years ago
Some features may on may not be enabled on cpu implementations. For example, I use my own ez80 implementation (z80 mode only) with sli, but without in f,(c), out (c),0, and all FD/DD CB dd xx. R800 supports in f,(c), but do not sli and others. So putting all these ops under one flag will cause later refactoring.
Also, I try to implement AsmParser but codegen causes lot of errors.
Also this patch contains fix for requirements for TST instruction (it is documented since Z180).