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jaijeet / VAPP

The Berkeley Verilog-A Parser and Processor
https://github.com/jaijeet/VAPP/wiki
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some minor issues in VAPP #10

Open wang159 opened 7 years ago

wang159 commented 7 years ago
  1. Analog function with multiple "input"/"output" statement lines

    Now, for functions with multiple "input"/"output" statements such as

analog function qj; input a input b ......

translates to ModSpec correctly. Before, the parser overwrites the "input" statements.

  1. Macros line numbers

    Before, all instances of macros are referred to line #1. This has been corrected to show the true line number of these macros

  2. Improved error handling in VAPP

    All errors in VAPP (frontend, backend, Lint errors, etc.) are now redirected to a unified VAPP_error() function. Fatal errors do not result in an abrupt stop any more; instead, issues catch up to that point is dumped into output, and error is displayed.

  3. Hidden/undeclared variables

    VAPP does not check is a variable at the RHS has already been assigned a value or not. This is not really an issue in VAPP, because I can see that ModSpec automatically initialize variables to 0. However, this can potentially cause problems for people who want to use VAPP to compile to C, for example. Now, any undeclared variable, or conditionally declared variables that may not get assigned value is caught and warning is given.

Now.....for things that you all may not like :)

  1. Allow reference-to-ground

    Previously, any reference-to-ground such as "V(node1)" abruptly stops VAPP. I find this too strict for two reasons: 1) Many Verilog-A scripts use reference-to-ground, and I would like to catch them all rather than letting VAPP stops one-at-a-time. 2) thermal and other disciplines may allow reference to an absolute ground.

to remedy this issue, if a reference-to-ground is caught, warning is given, and a new terminal associated with the discipline of the reference-to-ground node is spawned. For example, if an electrical node (node1) is referencing to ground, a new terminal node (vapp_gnd_electrical) is created. A branch (node1 to vapp_gnd_electrical) is also created. Only 1 universal ground is spawned for a certain disciplines.

  1. Node collapsing speed-up

    This is a very hard choice for me. At the moment, conditionals really give VAPP a difficult time, because each conditional spawns an additional branch of the tree that is dealing node collapsing. Uwjal's GaN HEMT model, for example, frequently use conditionals to collapse nodes, and it took over 3 hours to turn his model into ModSpec. I assigned a unique ID to each node, and use matrix operation to generate A(i,j) through (ID) matrix division. Similarly, for getOrderBranchVec(), logical matrix operations are used. Overall, parsing time is decreased.