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jaijeet / VAPP

The Berkeley Verilog-A Parser and Processor
https://github.com/jaijeet/VAPP/wiki
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Error where read verilog file #11

Open georgtree opened 1 year ago

georgtree commented 1 year ago

Hello! I got this error for code: error: Number of outputs does not match the number of children! error: called from get_child_names at line 276 column 17 visitBranch at line 184 column 38 visit at line 141 column 25 traverseAst at line 79 column 17 traverseChildren at line 99 column 27 traverseAst at line 88 column 17 visitRoot at line 110 column 20 visit at line 79 column 25 traverseAst at line 79 column 17 generateIrTree at line 72 column 20 AstVisitorIrGenerator at line 57 column 17 va2modspec at line 146 column 8

Code is write, compiled and work in different commercial simulators, also no warnings in VAlint.

Thank you in advance!

dwarning commented 1 year ago

I am not the author. There is a Readme.txt in the examples folder about Verilog-A limitations in VAPP: no global ground and other. Making this changes the model runs in VAPP/MAPP but they are not compatible any more with other compiler. Which model you have used?

gegen2000 commented 1 week ago

how to modify the va file to get arround the problem? Need I change the current variables at the same time. For example in my va file , I(di)<+V(ri)/R; need i change them all to I(di, bulk)<+V(ri, bulk)/R; Thanks