Support for different transfer size

jakubcabal / spi-fpga

SPI master and SPI slave for FPGA written in VHDL

MIT License

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Support for different transfer size #1

Closed keesj closed 3 years ago

keesj commented 6 years ago

Hi,

I have experimented with your code a little. I find it nice to read and learn from. For my purpose I need a larger transfer size (16 bits) perhaps that support for common transfer size (8,16,24,32) can be added?

jakubcabal commented 6 years ago

Hi, I plan to add support for different transaction sizes in the next version (perhaps this month) as VHDL generic.

keesj commented 3 years ago

Nice