Not working on Cyclone II

[lucagessi]

Hi. I am trying to work with this library using an Altera Cyclone II, working at 50 Mhz. I use an arduino as master. For debug I set a sclk of 100Khz or similar. Arduino sends clock and data but miso does not change. I have set data DIN_VLD to true and set a constant value of DIN input.

Nothing is received. Thank you

[jakubcabal]

Hi, do you have CS_N set to GND? And SCLK is without parasitic peaks, which could cause poor edge detection? You can try a Signal Tap (part of Quartus) to debug the signals inside the FPGA.

[lucagessi]

I saw sclk signal with oscilloscope and it was clear. I have never used signaltap. I though that the different voltage level (5v and 3.3v) could be a problema but I have made a simple test: I output on MISO a Square wave and Arduino reports a varing data as expected. So Yes, maybe the there is something wrong on signal.

Il sab 4 ago 2018, 08:12 Jakub Cabal notifications@github.com ha scritto:

Hi, do you have CS_N set to GND? And SCLK is without parasitic peaks, which could cause poor edge detection? You can try a Signal Tap (part of Quartus) to debug the signals inside the FPGA.

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[jakubcabal]

Yes, different voltage level could be a problem. Your test check only one direction (FPGA -> Arduino), right? But problem can be on oppostite direction. You can try simple voltage divider from resistors for voltage conversion from 5V to 3.3V (Arduino -> FPGA).

[lucagessi]

I don't think that It is real a problem. I have used an other library for i2c and it works perfectly. It uses however debounce on input pins.

Il sab 4 ago 2018, 08:53 Jakub Cabal notifications@github.com ha scritto:

Yes, different voltage level could be a problem. Your test check only one direction (FPGA -> Arduino), right? But problem can be on oppostite direction. You can try simple voltage divider from resistors for voltage conversion from 5V to 3.3V (Arduino -> FPGA).

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/jakubcabal/spi-fpga/issues/4#issuecomment-410428855, or mute the thread https://github.com/notifications/unsubscribe-auth/AFQfAmkTbGXSV_RHlyHMz7xXzFEl6HWfks5uNUTPgaJpZM4Vu3Ak .

[jakubcabal]

Also try SignalTap tool, then we will see the signals inside the FPGA and what is wrong. Some tutorials about SignalTap: http://pages.hmc.edu/harris/class/e155/SignalTap.pdf http://scale.engin.brown.edu/classes/EN164S17/SignalTap.pdf

[lucagessi]

Hi. Thanks you for your suggestion. That tool is really useful. Sclk signal is read right. The same for mosi. Smiso is internal signal connected to miso. That seems always the be same value. Why the name of this signal is red estead of blue? Thanks

Il sab 4 ago 2018, 09:12 Jakub Cabal notifications@github.com ha scritto:

Also try SignalTap tool, then we will see the signals inside the FPGA and what is wrong. Some tutorials about SignalTap: http://pages.hmc.edu/harris/class/e155/SignalTap.pdf http://url http://scale.engin.brown.edu/classes/EN164S17/SignalTap.pdf http://url

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[jakubcabal]

Please send me some screenshoots from SignalTap with the waveforms of all i/o SPI Slave ports and the waveforms of these internal signals: spi_clk_redge_en, spi_clk_fedge_en, bit_cnt_max, load_data_en, slave_ready, shreg_busy, rx_data_vld.