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jakubcabal / spi-fpga

SPI master and SPI slave for FPGA written in VHDL
MIT License
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Possible Meta-Stability Issue in Slave Module #5

Closed daveythacher closed 3 years ago

daveythacher commented 5 years ago

The clock signal can potentially trigger meta-stability conditions.

Example is driving SCK from external pin while using significantly faster internal clock. Granted the internal versus external does not matter, however the setup time difference can cause metastable condition to exist. A hardware solution may prevent this using something like a Schmitt trigger.

I have only tried using the slave module on a Lattice Macho XO2. I was using a test signal of about 100kHz and an internal clock of about 133MHz. Simply adding a two register metastability circuit appeared to fix it. (I have only done limited testing with it.) I think this should probably be at least a feature given the amount of control signals that are derived from the ability to detect clock edges.

jakubcabal commented 5 years ago

In my case, this problem did not show, but you're right. I will add a sync FFs to the next version of the SPI modules.