spi slave in hw => dout_vld no creating '1' value

[imuguruza]

Hi again,

After the simulation, I am implementing a simple spi slave in a Altera FPGA. I have wrapped the slave around a top module to assign pins. I have realized that the spi_slave does not rise the dout_vld flag:

I am using the next config:

• CLK of 50Mhz
• SPI SCLK of 5MHz.
• I am using 16bit of data MOSI in each spi transaction.

I have performed a less sofisticated spi_slave_tb gate-level simulation inspired in yours, and looks to be fine. I have plugged the Signal Tap Logic Analyzer and realize that the main difference is how MOSI behaves, in my case, its idle state is always '1':

Simulation capture:

I don't get why data_vld flag does not rise to '1' after each transaction... :thinking: :thinking:

[jakubcabal]

Hi,

can you please capture the following signals using signaltap? spi_clk_fedge_en, spi_clk_redge_en, bit_cnt, last_bit_en

[imuguruza]

It looks like fedge is not being detected:

I will have closer look...

edited the capture I have uploaded was wrong... Now I am sending just 8 bits, the "standard" data field

[jakubcabal]

Hi,

it looks like a problem with reset. spi_clk_reg is still in low, so is probably still in reset state. What is the RST signal value? My implementation uses reset active in high.

[imuguruza]

Hey you were right, I assigned the reset pin into an input not used. So the value read was '1'. not allowing a proper function of the design. I have assigned the reset to '0' value and now is working fine. Thanks for your support!