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1 year ago it is not only possible, it is a great idea. if one J1 is better than one register machine, imagine how much better a whole bunch of J1s would be.
The DE10 Nano board, uses the Intel Cyclone® V SE 5CSEBA6U23I7 device ( with 110K LEs). The J1 reqires 70 Luts without a barrel shifter, 150 with, so if an LE is the same thing as a lut, you could fit a whole bunch of J1s on such a board. Of course you also need networking.
The more important question is what exactly do you intend to do with it? You mentioned robotics. Do you have a specific robot in mind? How many motors do you need to control? How many sensors do you need to read? What is the speed, and bandwidth of the sensors and motors? What control algorithms do you plan to implement? What cross talk would there be between the nodes. How many J1's would you require?
In practice everyone I talk to says that robots are slow, you can control them with just software. On the other hand, for control of motors, it greatly simplifies life if each motor can have its own processor, then no need for interrupts, and managing the complexities of responding in real time. One person I know controls 14 motors with FPGA's. Easy if you are a verilog engineer, for the average software engineers, a CPU with 16 J1 cores would be way easier to configure.
In general I think that this is a very interesting area, but no one else seems to think so. My postings on Google groups comp.lang.forth have met with minimal responses. The FPGA engineers prefer to do everything in verilog. the software engineers are happy staying on traditional microcontrollers.There are just not that many people interested in Forth processors. Even fewer are interested in multiple Forth cores. What is missing is a killer app.
The two interesting competitors are the Parallax Propeller, and the XMOS devices. The parallax machine has 8 32 bit register machines which come with Forth, but each have only 1024 longs of memory. Every 8th clock cycle each processor gets access to the larger shared memory and cordic functions. The XMOS has multiple cores, each of which has multiple register sets. The XMOS does all of its I/O by bitbanging IO pins. Their new marketing pitch is AI for IoT.
The verilog is the easy part. The hard part is to find an application where multiple J1's would be economically competitive.
Can I please ask if you think it viable to use your J1 code to create a GA like device in FPGA? Would it, in your opinion, be a massive amount of effort?
My hope would be to use something like the above on a DE10 nano board such that the arm processor controls the array and/or allocates work to individual nodes.
The use case here would be for robotics acceleration and/or ML testing where having a large number of Forth processors working in parallel would be advantageous.
Thanks in advance for any advice or answers!