Closed bmentink closed 6 years ago
Sounds interesting - will you be publishing the source?
I don't know of any ways to improve j1b's timing. As I recall I'd already tried to optimize its paths as much as possible.
I am happy to provide the source, when I get it all together and documented.
However, this should be a two-way street, you are very hard to contact. If I am to donate the code, then I would expect that to change .... ;) (I have asked you a number of questions in the past and have been ignored ..)
You are welcome to fork the repo, then you can decide how much time to devote to supporting an open-source project.
OK to close this issue?
Ok, get the hint. You don't want to put in any more time :) I will contribute to an existing fork of your code that is well supported ..
Cheers, and have a great day.
PS: Close away ....
Hi James,
I don't know if you are still contactable or if this project is still active, but I have posted this just in case are still interested.
I have j1b running at 80Mhz on both Spartan-6 and Artix-7 boards - it will run at 100Mhz (just) on the Artix-7, but borderline as there is timing issues on the ram dstack .... Is there a way to improve this?
Also for your interest, I have implemented a number of Floating point hardware modules in verilog and interfaced them to Forth (F+,F-,F*,F/ and F-inverse-sqrt) They all happen in less than 3 clock cycles.
On Artix-7 Forth + FP takes up 3500 LUT's .......