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jamesbowman / swapforth

Swapforth is a cross-platform ANS Forth
BSD 3-Clause "New" or "Revised" License
275 stars 55 forks source link

ram.v for ice40UP5k #56

Closed igor-m closed 6 years ago

igor-m commented 6 years ago

Hi, I've got an ice40UP5k board and want to try with J1a(b). Is there any chance to get available a ready made "ram.v" with the basic words set? My current understanding is the ram.v is the same source for all 1k/4k/8k/UP5k chips. My intention is to get it working with IceCube2 under Win. Thanks

jamesbowman commented 6 years ago

Hmm, am having trouble looking up the ice40UP5 - do you have a link?

igor-m commented 6 years ago

http://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40Ultra.aspx ice40UP5k - Ultra Plus 5k - at the right hand side of the selection guide table

jamesbowman commented 6 years ago

Correct, the RAM contents should be possible.

With the correct J1a implementation in Verilog (including the UART pins hooked up) this should have a full set of words. It is a 4Kx16 RAM, contents in hex: nuc.hex.txt

Then you will want to replace this file:

https://github.com/jamesbowman/swapforth/blob/master/j1a/icestorm/j1a.v

with a version for IceCube2. Keep the j1, the UART, and hook up the RAM initialized with the above file. The IO ports won't apply to your board, so delete all that.

Hope this helps, J.

igor-m commented 6 years ago

Would it not be easier to have the "ram.v" source available (no need to run mkrom.py and gforth then)? You still need it in order to compile the j1a in Icecube2, afaik: j1.v + j1a.v + ram.v + uart.v + stack2.v