J1B does not compile with the newest Verilator 4.210 2021-07-07 rev v4.210-19-gde408a5e

When I try to compile J1B (via make in j1b/swapforth/j1b/verilator), I get the old error:

verilator --l2-name v -Wall -I../verilog/ --cc j1b.v ../verilog/j1.v ../verilog/stack.v --top-module j1b --exe sim_main.cpp
%Error: j1b.v:63:8: Duplicate declaration of signal: 'uart0_wr'
                  : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)
   63 |   wire uart0_wr = io_wr_ & io_addr_[12];
      |        ^~~~~~~~
        j1b.v:8:24: ... Location of original declaration
    8 |            output wire uart0_wr,
      |                        ^~~~~~~~
%Error: j1b.v:64:8: Duplicate declaration of signal: 'uart0_rd'
   64 |   wire uart0_rd = io_rd_ & io_addr_[12];
      |        ^~~~~~~~
        j1b.v:9:24: ... Location of original declaration
    9 |            output wire uart0_rd,
      |                        ^~~~~~~~
%Error: Exiting due to 2 error(s)
make: *** [Makefile:8: obj_dir/Vj1b] Error 1

it can be easily fixed as described in https://github.com/jamesbowman/swapforth/issues/67 - there is a commit https://github.com/wzab/swapforth/commit/4a705b0d44aaf532f68a378b27aefc85b47d1290 that can be cherry-picked to fix it. Afterwards the J1B builds with Verilator 4.038, but an attempt to build it with 4.210 still leads to an error:

verilator --l2-name v -Wall -I../verilog/ --cc j1b.v ../verilog/j1.v ../verilog/stack.v --top-module j1b --exe sim_main.cpp
make -C obj_dir CXXFLAGS="-fPIC" OPT_FAST="-O2" -f Vj1b.mk Vj1b
make[1]: Entering directory '/tmp/j1b/swapforth/j1b/verilator/obj_dir'
ccache g++ -fPIC -I.  -MMD -I/tmp/vrl/share/verilator/include -I/tmp/vrl/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow      -std=gnu++14 -O2 -c -o sim_main.o ../sim_main.cpp
../sim_main.cpp: In function 'int main(int, char**)':
../sim_main.cpp:23:12: error: 'class Vj1b' has no member named 'v__DOT__ram'
   23 |       top->v__DOT__ram[i] = v;
      |            ^~~~~~~~~~~
make[1]: *** [Vj1b.mk:61: sim_main.o] Error 1
make[1]: Leaving directory '/tmp/j1b/swapforth/j1b/verilator/obj_dir'
make: *** [Makefile:9: obj_dir/Vj1b] Error 2

The l2-name option does not help. Inspection of files generated in obj_dir shows that t he whole class structure has changed.

jamesbowman / swapforth

J1B does not compile with the newest Verilator 4.210 2021-07-07 rev v4.210-19-gde408a5e #72