Starting from Verilator version 4.210, the model class is an interface object. For reaching Verilog variables internal to a module this means that we need to include an extra header in cpp files that reference them (#include "Vj1a_024root.h"). And they're now part of a rootp class which is a member of the model class; we need to add an extra level of indirection. So 'top->vDOTram_prog[i] = v;' becomes 'top->rootp->vDOT__ram_prog[i] = v;'. See https://verilator.org/guide/latest/connecting.html for more words.
I don't know when these were introduced, but Verilator has become more strict about allowing assignments to wires. So 'insn' has become a reg as we assign to it inside a procedural block. And the 'wire uart0_(wr|rd) = ..' wire declarations on line 60/61 were duplicates of the module port declarations.
stuij
commented
1 year ago
Starting from Verilator version 4.210, the model class is an interface object. For reaching Verilog variables internal to a module this means that we need to include an extra header in cpp files that reference them (#include "Vj1a_024root.h"). And they're now part of a rootp class which is a member of the model class; we need to add an extra level of indirection. So 'top->vDOTram_prog[i] = v;' becomes 'top->rootp->vDOT__ram_prog[i] = v;'. See https://verilator.org/guide/latest/connecting.html for more words.
I don't know when these were introduced, but Verilator has become more strict about allowing assignments to wires. So 'insn' has become a reg as we assign to it inside a procedural block. And the 'wire uart0_(wr|rd) = ..' wire declarations on line 60/61 were duplicates of the module port declarations.