Self paths

[jameshanlon]

Eg.

$ ./install/bin/netlist-paths --compile ../tests/verilog/registered_output_path.sv --from out                         

Path 0
Name                       Type DType        Statement Location
-------------------------- ---- ------------ --------- --------
out                        REG  [31:0] logic                   
registered_output_path.out VAR  [31:0] logic                   
out                        REG  [31:0] logic                   

Path 1
Name                       Type DType        Statement Location
-------------------------- ---- ------------ --------- --------
out                        REG  [31:0] logic                   
registered_output_path.out VAR  [31:0] logic                   

Path 2
Name Type DType        Statement Location
---- ---- ------------ --------- --------
out  REG  [31:0] logic   

There should be no first path out -> out reported.

Related to #10

[jameshanlon]

Without register splitting:

With splitting:

Issue is that the three variables are all aliases of the same entity.

[jameshanlon]

This is improved with 9dedf78bb36dc234647fdfb816528db87a873f59, removing the last two paths in the above fan-out path list.