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jameshanlon / netlist-paths

A library and command-line tool for querying a Verilog netlist.
https://jameshanlon.github.io/netlist-paths
Apache License 2.0
26 stars 3 forks source link

Verilator cannot inline interfaces #16

Open jameshanlon opened 2 years ago

jameshanlon commented 2 years ago 
Running: "/Users/jamieh/netlist-paths/Debug/install/bin/np-verilator_bin" +1800-2012ext+.sv --bbox-sys --bbox-unsup --xml-only --flatten --error-limit 10000 --xml-output cb5uh292 ../tests/verilog/interface_no_inline.sv 
Parsing input XML file
Unrecognised node: ifacerefdtype
Unrecognised node: ifacerefdtype
Unrecognised node: ifacerefdtype
Type table contains 3 entries
Add var 'i_clk' to scope
Edge to/from original var VAR to VAR
Add var 'top.i_clk' to scope
Edge to/from original var VAR to VAR
Unrecognised node: instance
Unrecognised node: intfref
Unrecognised node: intfref
Unrecognised node: intfref
Add var 'top.bus_if__Viftop' to scope
Add var 'top.p.i_clk' to scope
Edge to/from original var VAR to VAR
Add var 'top.p.bus_if' to scope
Add var 'top.c.p_width' to scope
Add var 'top.c.i_clk' to scope
Edge to/from original var VAR to VAR
Add var 'top.c.bus_if' to scope
Add var 'top.c.valid_q' to scope
Add var 'top.c.data_q' to scope
New scope
New scope
New statement: ASSIGN
Edge from VAR 'i_clk' to LOGIC
Edge from LOGIC to VAR 'i_clk'
New statement: ASSIGN
Edge from VAR 'i_clk' to LOGIC
Edge from LOGIC to VAR 'i_clk'
New statement: ASSIGN
Edge from VAR 'top.i_clk' to LOGIC
Edge from LOGIC to VAR 'p.i_clk'
New statement: ASSIGN
Unrecognised node: const
Error: var valid does not have a VAR_SCOPE