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jameshegarty / rigel

Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
MIT License
56 stars 9 forks source link

Remove stall domains #107

Open jameshegarty opened 6 years ago

jameshegarty commented 6 years ago

Remove support for multiple stall domains from systolic? And then just implement the stuff that needs this (fifo) directly in verilog.