Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
Coverage increased (+0.04%) to 73.406% when pulling 9dc3eb8d3a51a163e815ddb1e7f0f472e419a894 on nonalignedrw into fdcce0f930de957ac4b6df1571ae94865b378782 on master.
Coverage increased (+0.04%) to 73.406% when pulling 9dc3eb8d3a51a163e815ddb1e7f0f472e419a894 on nonalignedrw into fdcce0f930de957ac4b6df1571ae94865b378782 on master.